The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	Hardware design for JPEG and a comparative study of JPEG and MPEG image compression algorithms
Author:	Soundararajan, Aravind
View Online:	njit-etd1993-144 (xi, 113 pages ~ 2.5 MB pdf)
Department:	Department of Electrical and Computer Engineering
Degree:	Master of Science
Program:	Electrical Engineering
Document Type:	Thesis
Advisory Committee:	Akansu, Ali N. (Committee chair) Bar-Ness, Yeheskel (Committee member) Cooper, David (Committee member)
Date:	1993-10
Keywords:	Data compression (Telecommunication) Image transmission. Microprocessors.
Availability:	Unrestricted
Abstract:	The complete PC-based hardware design along with the initialization and control software of the JPEG algorithm is presented in this thesis. The hardware could run in real-time to compress, decompress and display still frame images. LSI Logic JPEG chipset was used in the design. This is a dedicated chipset for the JPEG compression algorithm. A simulation software was used for studying the performance of MPEG video compression algorithm. Various video test sequences were compressed through the codec simulation software and the resulting rate-distortion performance was calculated. These are compared with the performance of JPEG based image sequence compressor. It is found that the MPEG-based video codec significantly outperforms the JPEG-based codec for the test sequences considered at low to medium bit rates.