Digital communications
Timing circuits
Synchronization
Availability:
Unrestricted
Abstract:
Many methods have been developed for evaluating the jitter performance of timing recovery circuits for binary synchronous transmission systems. These circuits consist of a nonlinear device followed by a narrowband filter tuned to the pulse repetition frequency. This thesis introduce delay shifts in the timing recovery circuits to improve the jitter performance. The function of the delay shifts is analyzed and mathematical proof of jitter performance improvement is given for the system using square-law device. Finally, the numerical results obtained from the specific examples serve to illustrate the significant improvement between the system with and without delay shifts. That is, one delay shift introduced in the system can gain nearly 3 db in rms jitter performance.
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