The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	Fault tolerant clos network
Author:	Ahluwalia, Preet Mohan S.
View Online:	njit-etd1991-075 (iv, 44 pages ~ 1.0 MB pdf)
Department:	Department of Electrical and Computer Engineering
Degree:	Master of Science
Program:	Electrical Engineering
Document Type:	Thesis
Advisory Committee:	Carpinelli, John D. (Committee chair) Robbi, Anthony D. (Committee member) Ziavras, Sotirios (Committee member)
Date:	1991-01
Keywords:	Fault-tolerant computing Computer network architectures Computer algorithms
Availability:	Unrestricted
Abstract:	Multistage interconnection networks, or MINs, provide paths between functional modules in multiprocessor systems. The MINs are usually segmented into several stages. Each stage connects inputs to appropriate links of the next stage so that the cumulative effect of all the stages satisfies input-output connection requirements. This thesis deals with a fault tolerant Clos network. The fault tolerance technique involves addition of extra switches per stage to compensate for any switch failure The reliability analysis of both ordinary and fault tolerant Clos networks is presented. The optimal number of extra switches required to get the best reliability results has been analyzed.