The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	Flash ADC using 2um CMOS P-well technology : design and test
Author:	Levinson, Joseph E.
View Online:	njit-etd1996-062 (ix, 55 pages ~ 2.4 MB pdf)
Department:	Department of Electrical and Computer Engineering
Degree:	Master of Science
Program:	Electrical Engineering
Document Type:	Thesis
Advisory Committee:	Carr, William N. (Committee chair) Lau, Siu Bor (Committee member) Sohn, Kenneth (Committee member)
Date:	1996-05
Keywords:	Analog-to-digital converters--Design. Analog-to-digital converters--Testing. Integrated circuits--Design. Metal oxide semiconductors, Complementary.
Availability:	Unrestricted
Abstract:	This thesis describes the design, implementation and test for a new CMOS analog-to-digital converter IC chip. In designing the analog-to-digital converter in this thesis a radically different comparator design that is only available with CMOS logic. The design utilizes a single CMOS inverter as an ultra-high gain amplifier. This approach reduces the circuit dependence upon matching of the transistors similar to the traditional method. This new design requires less area since the comparator utilizes fewer transistors. Flash analog-to-digital converters use 2" - 1 comparators to do a single conversion where n is the number of bits used. These comparators are traditionally made with differential transistor amplifiers in order to obtain matched characteristics. Effects of mismatch in current gains and base emitter voltage is reduced in the new design since the amplifier topology does not depend entirely upon perfectly matched transistors.