The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	Partial VLSI implementation of the architecture for reusable components (ARC)
Author:	Kakadasam, Deepak
View Online:	njit-etd1993-098 (xiv, 105 pages ~ 3.1 MB pdf)
Department:	Department of Electrical and Computer Engineering
Degree:	Master of Science
Program:	Electrical Engineering
Document Type:	Thesis
Advisory Committee:	Misra, Durgamadhab (Committee chair) Welch, Lonnie R. (Committee member) Kosonocky, Walter F. (Committee member)
Date:	1993-01
Keywords:	Integrated circuits -- Very large scale integration Computer software -- Reusability
Availability:	Unrestricted
Abstract:	This work describes a novel VLSI implementation of the Architecture for Reusable Components (ARC) processor, using Hardware Description Language (HDL). The main goal here is to achieve efficient execution of reusable software through proper hardware support. This involves the hard wired implementation of each instruction designed for the ARC processor. Instructions are broken down into their logical functions, then modeled and simulated through the hierarchical design methods that HDL offers. The structural model of the processor has been developed and simulated. The purpose here has been to begin work on the design and implementation of the ARC processor. The instructions were built using HDL modules, and then simulated using a logic simulator. The effect of internal propagation delays in the execution of the logic modules have been investigated. Changes in delay parameters have been applied to obtain correct logic transfer operations. The redundancy in the logic transfer operations have also been investigated to see parallelism at the instruction execution level.