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Title:	Study of deep level defects of N+-CdS/P-CdTe solar cells
Author:	Kharangarh, Poonam Rani
View Online:	njit-etd2013-076 (xix, 134 pages ~ 3.5 MB pdf)
Department:	Department of Physics
Degree:	Doctor of Philosophy
Program:	Applied Physics
Document Type:	Dissertation
Advisory Committee:	Chin, Ken K. (Committee co-chair) Georgiou, George E. (Committee co-chair) Delahoy, Alan E. (Committee member) Ravindra, N. M. (Committee member) Misra, Durgamadhab (Committee member) Schaden, Martin (Committee member)
Date:	2013-05
Keywords:	Current-voltage Capacitance-voltage Capacitance-time Temperature dependence CdTe solar cell
Availability:	Unrestricted
Abstract:	Among various photovoltaic materials, polycrystalline cadmium telluride thin film is now the most promising material, due to its low production cost excellent stability and reliability. Current-voltage and capacitance-voltage measurements of CdTe photovoltaic devices at different temperatures can provide valuable information about non-idealities in the n-p semiconductor junction. There are certain limitations which limit the efficiency of CdTe solar cells. There is no real distinction between defects and impurities in CdTe solar cells as both act as beneficial dopants or detrimental traps unlike Si where intentional shallow dopants and traps are distinctly different. Therefore, the role of defect states on CdTe solar cell performance, the effect of processing on defect states, and simple and effective characterization techniques must be investigated and identified. In this research the thin film n+-CdS/p-CdTe solar cells made with evaporated Cu as a primary back contact, are characterized by using the temperature dependence of the reverse bias diode current (J-V-T) to determine the energy levels of deep defects. The results of the J-V-T measurements on solar cells made at NJIT show that while modest amounts of Cu enhance cell performance, an excessive high temperature annealing step degrades device quality and reduces efficiency. This work addresses the error that can be introduced during defect energy level estimation if the temperature dependence of the carrier capture cross-section is neglected. Therefore, the location of traps is derived using a Shockley-Read-Hall recombination model with modified assumptions. A Cu-related deep level defect with activation energy of 0.57eV is observed for Cu evaporated back contact cells and an intrinsic defect with activation energy 0.89eV is found. Frequency dispersion in Capacitance-Voltage measurements confirms the presence of Cu-related deep level traps for cells with a Cu evaporated back contact, whereas no such defects are observed in carbon paste contact. The behavior is believed to be due to diffusion of excess Cu from the contact. It is further observed that majority carrier deep level traps (Cu-related or intrinsic) contribute differently to the degradation of electronic properties of the CdTe solar cells. A simple and effective characterization technique based on temperature dependent capacitance spectroscopy (TDCS) is used to identify majority carrier trapping defects in thin film n+-CdS/p-CdTe solar cell, made with evaporated Cu as a primary back contact. The distinct deep level traps, observed by TDCS seem to be due to the ionization of impurity centers located in the depletion region of n+-CdS/p-CdTe junction