The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	Development and evaluation of a simultaneous multithreading processor simulator
Author:	Nunez, Carla Verena S.
View Online:	njit-etd2007-038 (xi, 56 pages ~ 3.3 MB pdf)
Department:	Department of Electrical and Computer Engineering
Degree:	Master of Science
Program:	Computer Engineering
Document Type:	Thesis
Advisory Committee:	Hu, Jie (Committee co-chair) Ziavras, Sotirios (Committee co-chair) Carpinelli, John D. (Committee member)
Date:	2007-05
Keywords:	Processor architecture Simultaneous multithreading Computers
Availability:	Unrestricted
Abstract:	Modem processors are designed to achieve greater amounts of instruction level parallelism (ILP) and thread level parallelism (TLP). Simultaneous multithreading (SMT) is an architecture that exploits both LLP and TLP. It improves the utilization of the processor resources by allowing multiple independent threads to reside in the pipeline and dynamically scheduling the available resources among the threads. The first part of this thesis presents the development of a simultaneous multithreading processor simulator. The SMT simulator is derived from SimpleScalar, a superscalar processor simulator widely used in the computer architecture research field. The basic pipeline is expanded to allow multiple threads to be fetched, dispatched, issued, executed, and committed simultaneously. Benchmarks that were executed on the SMT simulator verified its functionality. The simulator produced the correct outputs and the performance levels achieved were similar to those produced by the original authors of the SMT architecture. The second part of this thesis explores the register file for SMT processors. The register file size grows with increased issue widths, instruction window sizes, and number of thread contexts; as the register file size increases, so does its access latency. Solutions to the register file problem have been proposed but most of these were designed for and evaluated on superscalar processors. The use-based register cache is one such design and its effectiveness on an SMT architecture is evaluated in this thesis. The SMT simulator is a useful tool for evaluating components designed for superscalar processors on a simultaneous multithreading environment and for testing future designs of SMT architectural elements.