With the rapid development in low-cost CMOS technology, silicon photodiodes are currently recognized as promising choice for the imager core. In this research, the arrays of back illuminated photodiodes were designed, fabricated and demonstrated with CMOS imager fabrication process on silicon wafers. The main purpose of this work was to improve the contribution of these arrays on the imaging systems before committing their design on the chips.
In this CMOS process, first the n-well, p-well, n+and p+ regions were simulated and fabricated by several implantation processes. The n-well region was implanted by phosphorus at an energy of 170 keV and dose of 7x1012cm-2 to obtain a 1 μm deep well. p-well was implanted with boron at energy of 70 keV and dose of lxl013cm-2 with a depth comparable to n-well region. An annealing for 30 minutes was then held after completion of these two implantation steps to drive-in the dopants. Phosphorus implant (45 keV, 2x1014 cm-2) and boron implant (30 keV, 2x1014 cm-2) were made to form n+ and p+ regions respectively, with a depth around 0.4 μm. Some test structures were also designed during the device fabrication, to compare the sheet resistances with the simulated values of the implantation steps.
The dark current, simulated for the fabrication conditions, shows a value of 1 .95pA at a reverse bias of -3V. The measured dark current, just after metallization, had a value of 15pA with same applied bias.
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