The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	Characterization of ultrathin gate dielectrics and multilayer charge injection barriers
Author:	Dons, Edwin M.
View Online:	njit-etd2004-082 (xiv, 114 pages ~ 5.8 MB pdf)
Department:	Federated Physics Department of NJIT and Rutgers-Newark
Degree:	Doctor of Philosophy
Program:	Applied Physics
Document Type:	Dissertation
Advisory Committee:	Farmer, Kenneth Rudolph (Committee chair) Chin, Ken K. (Committee member) Tompa, Gary S. (Committee member) Wu, Zhen (Committee member) Xiao, Zhixiong (Committee member)
Date:	2004-05
Keywords:	Nonvolatile memory Gate dialectrics Ultrathin oxide Layered tunnel barrier Oxide degradation Electron tunneling
Availability:	Unrestricted
Abstract:	Since the invention of the first integrated circuit, the semiconductor industry has distinguished itself by a phenomenally rapid pace of improvements in device performance. This trend of ever smaller and faster devices is a result of the ability to exponentially reduce feature sizes of integrated circuits, a trend commonly known as "scaling". A reduction of overall feature sizes requires a simultaneous reduction in the thickness of the gate dielectric, SiO2, of a MOSFET. Gate oxides in the ultrathin regime (<35 A) feature a large direct tunneling leakage current. The presence of this leakage current requires a reevaluation of standard characterization techniques as well as a reevaluation of the continued usefulness of SiO2 as the gate dielectric of choice for future applications. On the other hand, a thorough understanding of the dynamics of ultrathin oxides opens up a range of future device applications that were not possible with thicker oxides. Capacitance-voltage characterization has been the standard technique to study the electrical properties and interface quality of MOS devices. However, the presence of a large leakage current in ultrathin oxides distorts standard C-V measurements, rendering this technique no longer useful. In this work, a leakage compensated charge measurement is developed to overcome this difficulty. This technique produces static C-V curves, even for oxides as thin as 24 A, thereby permitting C-V characterization well into the direct tunneling regime. As an extension of this leakage problem, the usefulness of SiO2 as the gate dielectric of choice for future CMOS devices has been called into question. One solution - but not the only - calls for a new dielectric to replace SiO2 for future gate applications. This research presents some of the earliest results ever on the electrical properties of MOCVD and ALCVD hafnium oxides as a potential candidate. Electrical characterization revealed that the devices have characteristics such as large leakage currents, dielectric charging under stress, hysteresis and a large flatband voltage shift that is commonly found in materials such as the one that was investigated in this work. As one example of future device applications that become possible due to the scaling of ultrathin oxides, silicon-based multilayer charge injection barriers have been investigated. These barriers consist of alternating layers of ultrathin SiO2 and Si. The electrical properties of these structures were studied in detail and revealed that they can be used as an active tunnel dielectric in nonvolatile memory devices.