This thesis studied the plasma-induced damage to Si and strained Si1-xGex, and the resulting change in device characteristics. The energetic particles (ions, electrons and photons) in plasma reactor present a potentially hostile environment for processing VLSI devices. An inductively coupled plasma (ICP) reactor was used to study its damage effects to thin gate oxides. Electrical characterizations by C-V, ramped voltage breakdown (RVB) and deep-level transient spectroscopy (DLTS) measurement, and x-ray photoelectron spectroscopy (XPS) analysis were employed to investigate the damages to thin gate oxides and Si/SiO2 interface. The shift of flat band voltage, the reduction of breakdown voltage and the creation of high interface trap density were found to be in good agreement with the creation of suboxidation states at Si/SiO2 interface. It is observed that device damage is well associated with the reactor operating conditions. The major mechanism responsible for damage appeared to be high energy electron charging which occurred when only the ICP power was activated, without any rf bias to the wafercarrying electrode. Energetic particle bombardment damage was dominant when the wafer-carrying electrode'was biased and the damage was considerably higher for rf bias power grater than 35W.
The effect of plasma processing to the strained Si1-xGex layer of p+ - n diode has been investigated. The effect of SF6 plasma, used to etch an overlying Si film stopping at the strained Si1-xGex film, on the electrical properties of an underlying Si1-xGex/Si heterojunction device was studied. The changes of C-V and I-V characteristics, such as higher depletion capacitance and lower diffusion current were attributed to ion bombardment and radiation-induced bonding change, such as creation of interface charges and recombination centers. The TEM analysis revealed the dislocation loops in Si/Si1-xGex/Si outside the aluminum contact region due to the ion bombardment stress. The O2 plasma ashing has moderate effect to Si1-xGex device when the device was protected by aluminum contact layer.
The C-V profiling techniques on SiGe MOS structures were used to investigate the change of valence band discontinuity (ΔEv) at the Si/SiGe interface before and after plasma exposure and high temperature annealing. Wet and plasma etched samples were annealed at 500, 600, 700 and 800°C for 60 seconds. It was observed that the accuracy of extracting the changes of ΔEv using the C-V profiling was strongly influenced by the release of electrons from the traps at SiO2/Si interface, which were created during the low-pressure CVD SiO2, deposition. The device simulations have been used to confirm this finding. By carefully analyzing the C-V profile at slight depletion region the band gap modifications at back Si/SiGe interface due to process-induced damage could be evaluated. The dry etched sample was partially relaxed after 700°C annealing while wet etched sample was partially relaxed after 800°C annealing. Dry etched sample demonstrated a faster relaxation mechanism as compared to its wet etched counterpart due to the creation of dislocation loops by dry etching process. The C-V method is a simple, fast and efficient approach to estimate any band-gap modification in SiGe due to process-induced damage, but the measurements and simulations in slight depletion region should be carried out with special care and high resolution.
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