The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	The study of SiGe-channel heterojunction MOS device
Author:	Qiu, Yunchen
View Online:	njit-etd1996-020 (xiii, 94 pages ~ 5.4 MB pdf)
Department:	Department of Electrical and Computer Engineering
Degree:	Master of Science
Program:	Electrical Engineering
Document Type:	Thesis
Advisory Committee:	Misra, Durgamadhab (Committee chair) Sohn, Kenneth (Committee member) Cornely, Roy H. (Committee member)
Date:	1996-05
Keywords:	Metal oxide semiconductors--Junctions
Availability:	Unrestricted
Abstract:	The advances in the growth of pseudomorphic silicon-germanium epitaxial layer combined with the strong need for high-speed CMOS VLSI circuit have led to increased interest in silicon-based heterojunction MOSFET's transistors. The high-performance heterostructure SiGe MOSFET exhibits higher channel mobility than its bulk Si counterpart. The most critical and challenging process for fabricating a SiGe MOSFET device is that for making a gate oxide with sufficient quality for useful conductivity modulation. PECVD methods was employed to deposit the gate oxide and C-V method was used to investigate the electrical characteristics of the film. For PECVD gate oxide, a film refractive index 1.47 were obtained using the deposition rate 125Å/min with a break down voltage 4-5 MV/cm, which deposition conditions are optimized as flow rate of DES (12sccm), N20(172sccm), Helium(850sccm), temperature 300°C, power density 0.09W/cm2. The total interface trap and fixed charge density Nt=5.4x1012 cm-2 and flatband voltage Vfb=-16V for non-armealing MOS capacitor and the total effect of interface trap and fixed charge density 6.4x1011 cm-2 and flatband voltage 4V were obtained at the oxide thickness dox=1160Å using annealing at 650°C for 30 minutes in the ambient of nitrogen. LPCVD silicon dioxide film was obtained at the deposition rate 14.5 Å/min and refractive index 1.46 while Nt=3.9x1012cm-2 and Vfb=-8V for nonannealing and Nt=4.9x1011 cm-2 and Vfb=-2V for 650°C annealed MOS capacitor.