The New Jersey Institute of Technology's
Electronic Theses & Dissertations Project

Title:	Fault-tolerant interconnection networks for multiprocessor systems
Author:	Nassar, Hamed Mohamed
View Online:	njit-etd1989-034 (viii, 130 pages ~ 5.1 MB pdf)
Department:	Department of Electrical and Computer Engineering
Degree:	Doctor of Engineering Science
Program:	Electrical Engineering
Document Type:	Dissertation
Advisory Committee:	Carpinelli, John D. (Committee chair) Misra, Raj Pratap (Committee member) Ng, Peter A. (Committee member) Robbi, Anthony D. (Committee member)
Date:	1989
Keywords:	Fault-tolerant computing. Computer organization.
Availability:	Unrestricted
Abstract:	Interconnection networks represent the backbone of multiprocessor systems. A failure in the network, therefore, could seriously degrade the system performance. For this reason, fault tolerance has been regarded as a major consideration in interconnection network design. This thesis presents two novel techniques to provide fault tolerance capabilities to three major networks: the Baseline network, the Benes network and the Clos network. First, the Simple Fault Tolerance Technique (SFT) is presented. The SFT technique is in fact the result of merging two widely known interconnection mechanisms: a normal interconnection network and a shared bus. This technique is most suitable for networks with small switches, such as the Baseline network and the Benes network. For the Clos network, whose switches may be large for the SFT, another technique is developed to produce the Fault-Tolerant Clos (FTC) network. In the FTC, one switch is added to each stage. The two techniques are described and thoroughly analyzed.